Reply to thread

Message

<blockquote data-quote="chick3n0x07CC" data-source="post: 739951">I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests for a clock signal if it does make any sense at all.[CODE]-- hearbeat.vhdllibrary ieee;&nbsp; use ieee.std_logic_1164.all;entity HEARTBEAT is&nbsp; port (&nbsp; &nbsp; LEVEL : out&nbsp;&nbsp; std_logic&nbsp; );end entity HEARTBEAT;architecture RTL of HEARTBEAT is&nbsp; constant clk_period : time := 10 ns;begin&nbsp; -- Clock process definition&nbsp; CLK_PROCESS : process is&nbsp; begin&nbsp; &nbsp; LEVEL &lt;= &#039;0&#039;;&nbsp; &nbsp; wait for clk_period / 2;&nbsp; &nbsp; LEVEL &lt;= &#039;1&#039;;&nbsp; &nbsp; wait for clk_period / 2;&nbsp; end process CLK_PROCESS;end architecture RTL;[/CODE]Edit: I come from a software background where is common that each component/unity/entity you create has an associated set of tests, doesn&#039;t mind how simple they are. I&#039;m new to VHDL and I learned that each entity can be tested by creating a test bench. So my way of working until now was:Create an entity called X_CHIP (pseudo-code):[CODE]-- x_chip.vhdllibrary IEEE;&nbsp; use ieee.std_logic_1164.all;entity X_CHIP is&nbsp; port (.. port definition ..);end entity X_CHIP;architecture RTL of X_CHIP isbegin&nbsp; .. architecture definition ..end architecture RTL;[/CODE]How I test X_CHIP (pseudo-code):[CODE]-- x_chip_tb.vhdl. Notice it is a different filelibrary IEEE;&nbsp; use ieee.std_logic_1164.all;entity X_CHIP_TB isend entity X_CHIP_TB; -- emptyarchitecture BEHAVIOR of X_CHIP_TB is -- not the architecture of X_CHIP but X_CHIP_TB&nbsp; component X_CHIP is&nbsp; &nbsp; port (.. port definition ..);&nbsp; end component;&nbsp; .. signal declarations ..begin&nbsp; DUT_1 : entity work.X_CHIP(rtl)&nbsp; &nbsp; port map (.. port map definition ..);&nbsp; STIMULUS : process is&nbsp; begin&nbsp; &nbsp; &nbsp; assert .. report .. severity&nbsp; -- the tests themselves&nbsp; &nbsp; &nbsp; wait;&nbsp; end process STIMULUS;end architecture BEHAVIOR;[/CODE]That&#039;s why I thought the entity HEARTBEAT should have tests as well (a heartbeat_tb.vhdl file). But after reading some answers it seems that it makes no sense.</blockquote>

[QUOTE="chick3n0x07CC, post: 739951"] I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests for a clock signal if it does make any sense at all. [CODE]-- hearbeat.vhdl library ieee; use ieee.std_logic_1164.all; entity HEARTBEAT is port ( LEVEL : out std_logic ); end entity HEARTBEAT; architecture RTL of HEARTBEAT is constant clk_period : time := 10 ns; begin -- Clock process definition CLK_PROCESS : process is begin LEVEL <= '0'; wait for clk_period / 2; LEVEL <= '1'; wait for clk_period / 2; end process CLK_PROCESS; end architecture RTL; [/CODE] [B]Edit:[/B] I come from a software background where is common that each component/unity/entity you create has an associated set of tests, doesn't mind how simple they are. I'm new to VHDL and I learned that each entity can be tested by creating a test bench. So my way of working until now was: Create an entity called X_CHIP (pseudo-code): [CODE]-- x_chip.vhdl library IEEE; use ieee.std_logic_1164.all; entity X_CHIP is port (.. port definition ..); end entity X_CHIP; architecture RTL of X_CHIP is begin .. architecture definition .. end architecture RTL; [/CODE] How I test X_CHIP (pseudo-code): [CODE]-- x_chip_tb.vhdl. Notice it is a different file library IEEE; use ieee.std_logic_1164.all; entity X_CHIP_TB is end entity X_CHIP_TB; -- empty architecture BEHAVIOR of X_CHIP_TB is -- not the architecture of X_CHIP but X_CHIP_TB component X_CHIP is port (.. port definition ..); end component; .. signal declarations .. begin DUT_1 : entity work.X_CHIP(rtl) port map (.. port map definition ..); STIMULUS : process is begin assert .. report .. severity -- the tests themselves wait; end process STIMULUS; end architecture BEHAVIOR; [/CODE] That's why I thought the entity HEARTBEAT should have tests as well (a [I]heartbeat_tb.vhdl[/I] file). But after reading some answers it seems that it makes no sense. [/QUOTE]

Name

Verification