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How to write tests for a clock signal
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<blockquote data-quote="chick3n0x07CC" data-source="post: 739951"><p>I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests for a clock signal if it does make any sense at all.</p><p></p><p>[CODE]-- hearbeat.vhdl</p><p></p><p>library ieee;</p><p> use ieee.std_logic_1164.all;</p><p></p><p>entity HEARTBEAT is</p><p> port (</p><p> LEVEL : out std_logic</p><p> );</p><p>end entity HEARTBEAT;</p><p></p><p>architecture RTL of HEARTBEAT is</p><p></p><p> constant clk_period : time := 10 ns;</p><p></p><p>begin</p><p></p><p> -- Clock process definition</p><p> CLK_PROCESS : process is</p><p> begin</p><p></p><p> LEVEL <= '0';</p><p> wait for clk_period / 2;</p><p> LEVEL <= '1';</p><p> wait for clk_period / 2;</p><p></p><p> end process CLK_PROCESS;</p><p></p><p>end architecture RTL;</p><p>[/CODE]</p><p></p><p><strong>Edit:</strong> I come from a software background where is common that each component/unity/entity you create has an associated set of tests, doesn't mind how simple they are. I'm new to VHDL and I learned that each entity can be tested by creating a test bench. So my way of working until now was:</p><p></p><p>Create an entity called X_CHIP (pseudo-code):</p><p></p><p>[CODE]-- x_chip.vhdl</p><p></p><p>library IEEE;</p><p> use ieee.std_logic_1164.all;</p><p></p><p>entity X_CHIP is</p><p> port (.. port definition ..);</p><p>end entity X_CHIP;</p><p></p><p>architecture RTL of X_CHIP is</p><p>begin</p><p> .. architecture definition ..</p><p>end architecture RTL;</p><p>[/CODE]</p><p></p><p>How I test X_CHIP (pseudo-code):</p><p></p><p>[CODE]-- x_chip_tb.vhdl. Notice it is a different file</p><p></p><p>library IEEE;</p><p> use ieee.std_logic_1164.all;</p><p></p><p>entity X_CHIP_TB is</p><p>end entity X_CHIP_TB; -- empty</p><p></p><p>architecture BEHAVIOR of X_CHIP_TB is -- not the architecture of X_CHIP but X_CHIP_TB</p><p> component X_CHIP is</p><p> port (.. port definition ..);</p><p> end component;</p><p></p><p> .. signal declarations ..</p><p></p><p>begin</p><p> DUT_1 : entity work.X_CHIP(rtl)</p><p> port map (.. port map definition ..);</p><p></p><p> STIMULUS : process is</p><p> begin</p><p> assert .. report .. severity -- the tests themselves</p><p> wait;</p><p> end process STIMULUS;</p><p>end architecture BEHAVIOR;</p><p>[/CODE]</p><p></p><p>That's why I thought the entity HEARTBEAT should have tests as well (a <em>heartbeat_tb.vhdl</em> file). But after reading some answers it seems that it makes no sense.</p></blockquote><p></p>
[QUOTE="chick3n0x07CC, post: 739951"] I am using GHDL to create an entity called HEARTBEAT, which is a simple clock signal. I already wrote some testbench for other entities like AND or NOT gates. Now I am wondering how can I write tests for a clock signal if it does make any sense at all. [CODE]-- hearbeat.vhdl library ieee; use ieee.std_logic_1164.all; entity HEARTBEAT is port ( LEVEL : out std_logic ); end entity HEARTBEAT; architecture RTL of HEARTBEAT is constant clk_period : time := 10 ns; begin -- Clock process definition CLK_PROCESS : process is begin LEVEL <= '0'; wait for clk_period / 2; LEVEL <= '1'; wait for clk_period / 2; end process CLK_PROCESS; end architecture RTL; [/CODE] [B]Edit:[/B] I come from a software background where is common that each component/unity/entity you create has an associated set of tests, doesn't mind how simple they are. I'm new to VHDL and I learned that each entity can be tested by creating a test bench. So my way of working until now was: Create an entity called X_CHIP (pseudo-code): [CODE]-- x_chip.vhdl library IEEE; use ieee.std_logic_1164.all; entity X_CHIP is port (.. port definition ..); end entity X_CHIP; architecture RTL of X_CHIP is begin .. architecture definition .. end architecture RTL; [/CODE] How I test X_CHIP (pseudo-code): [CODE]-- x_chip_tb.vhdl. Notice it is a different file library IEEE; use ieee.std_logic_1164.all; entity X_CHIP_TB is end entity X_CHIP_TB; -- empty architecture BEHAVIOR of X_CHIP_TB is -- not the architecture of X_CHIP but X_CHIP_TB component X_CHIP is port (.. port definition ..); end component; .. signal declarations .. begin DUT_1 : entity work.X_CHIP(rtl) port map (.. port map definition ..); STIMULUS : process is begin assert .. report .. severity -- the tests themselves wait; end process STIMULUS; end architecture BEHAVIOR; [/CODE] That's why I thought the entity HEARTBEAT should have tests as well (a [I]heartbeat_tb.vhdl[/I] file). But after reading some answers it seems that it makes no sense. [/QUOTE]
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