G
Griffin Baker
I have read a few of the posts here regarding race conditions as they pertain to the RS Latch, but they don't answer my specific question. I understand that if the latch is given an invalid input like s=1, r=1, it will eventually settle to q and q' being 0 and 0.
What I don't get, however, is what happens when we give the latch its next "valid state". This is where the race condition plays out.
I understand that either q or q' will switch first. Let's say q switches first. This means that the input to the bottom latch with receive a 1. But the bottom latch was also in the act of sending a 1 signal to the top latch as well.
My question essentially is this: at the moment that the top latch's signal reaches the bottom NOR gate, is the signal it was sending (which was a 1, since both inputs were 0 previously) overridden? If not, how does this process actually play out?
Thank you!
What I don't get, however, is what happens when we give the latch its next "valid state". This is where the race condition plays out.
I understand that either q or q' will switch first. Let's say q switches first. This means that the input to the bottom latch with receive a 1. But the bottom latch was also in the act of sending a 1 signal to the top latch as well.
My question essentially is this: at the moment that the top latch's signal reaches the bottom NOR gate, is the signal it was sending (which was a 1, since both inputs were 0 previously) overridden? If not, how does this process actually play out?
Thank you!